1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of fabricating an isolation structure.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Typically, overall reduction in scale of the components of a typical transistor to increase the overall speed of the MOSFET or MOS transistor, and to increase the density, and number, of the transistors that can be produced on a given amount of wafer real estate, also requires a reduction in scale of the isolation structures that separate and electrically isolate semiconductor devices from each other. For example, in a CMOS device, an isolation structure is typically used to separate and electrically isolate the NMOS transistor from the PMOS transistor. It has proven difficult to form scaled-down isolation structures that reduce or eliminate charge-trapping in the isolation structures. It has also proven difficult to integrate the formation of isolation structures with the formation of gate dielectrics for MOS transistors, for example. Typically, isolation structures are disadvantageously exposed during subsequent processing, and this reduces the reliability of the isolation structures and of the semiconductor devices in which such isolation structures are contained.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.